Moo Sung Chae

Research Interest

Implantable integrated nerural recording system. (NEUREC)

Integrated spike sorting ciruits.

Wireless telemetry and clock recovery circuits for biomedical purpose

High-Bandwidth wave-pipelined datapath and its control circuits

<Layout of 16-channel neural recording system - NEUREC2. It has preamps, filters, an analog mux, and buffers to drive ADC. >

<Layout of variable resolution SAR ADC. It will be integrated in NEUREC3>

Education

University of California, Santa Cruz, Santa Cruz, CA, USA. September 2005 ~ current Pursuing Ph.D degree in electrical engineering
Seoul National University, Seoul, Korea. March 1998 ~ February 2000 M.S degree in electrical engineering.
Seoul National University, Seoul, Korea. March 1994 ~ February 1998 B.S degree in electrical engineering.
Gyeonggi High School, Seoul, Korea. March 1991 ~ February 1994.

Experience

Samsung Electronics, co.
Circuit Design Engineer. February 2000 ~ January 2005.
Korean Army
Enlisted in technical research personnel. April 2000 ~ December 2004.
Seoul National University
Teaching Assistant, March 1998 ~ June 1998, Electrical experiment.
Teaching Assistant, March 1999 ~ June 1999, Computer programming.

Publications

M. Chae, K. Chen, W. Liu, M. Sivaprakasam, J. Kim, "A 4-channel Wearable Wireless Neural Recording System", ISCAS 2008.

M. Chae, W. Liu, Z. Yang, T. Chien, J. Kim, M. Sivaprakasam, M. Yuce, "A 128-Channel 6mW Wireless Neural Recording IC with On-the-fly Spike Sorting and UWB transmitter", ISSCC 2008.

M.R. Yuce, W. Liu, M. Chae, J. Kim, “A Wideband Telemetry Unit for Multi-Channel Neural Recording Systems,” IEEE ICUWB, pp. 612-617, September 2007.

"A Multi-Channel Neural Recording System for Monitoring Shark Behavior,"
W. Liu, M. Sivaprakasam, G. Wang, and M. Chae, IEEE International Symposium on Circuits and Systems, May 2006.

"A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques"
Churoo Park; HoeJu Chung; Yun-Sang Lee; Jaekwan Kim; JaeJun Lee; Moo-Sung Chae; Dae-Hee Jung; Sung-Ho Choi; Seung-young Seo; Taek-Seon Park; Jun-Ho Shin; Jin-Hyung Cho; Seunghoon Lee; Ki-Whan Song; Kyu-Hyoun Kim; Jung-Bae Lee; Changhyun Kim; Soo-In Cho, IEEE Journal of Solid State Circuits

" A 512 Mbit, 1.6 Gbps/pin DDR3 SDRAM prototype with C/sub 10/ minimization and self-calibration techniques,"
Churoo Park; HoeJu Chung; Yun-Sang Lee; Jaekwan Kim; JaeJun Lee; Moo-Sung Chae; Dae-Hee Jung; Sung-Ho Choi; Seung-young Seo; Taek-Seon Park; Jun-Ho Shin; Jin-Hyung Cho; Seunghoon Lee; Ki-Whan Song; Kyu-Hyoun Kim; Jung-Bae Lee; Changhyun Kim; Soo-In Cho, VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on, June 2005

"Digitally controlled DLL and I/O circuits for 500 MB/s/pin x16 DDR SDRAM"
J.B. Lee, K.H. Kim, S.B. Lee, O.G. Na, H.Y. Song, J.S. Lee, Z.H. Lee, K.W. Yeom, H.J. Chung, I.W. Seo, M.S. Chae, Y.H. Choi, S.I. Cho, Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International, 5-7 Feb.2001

"The characteristic potential method of noise calculation in multi-terminal homogeneous semiconductor resistors"
C.H. Park, Y.S. Kim, M.S. Chae, J.S. Kim, H.S. Min, Y.J. Park, J.Phys. D:Appl. Phys. 35. March 2002.

"A general approach for calculation of thermal noise currents in semiconductor devices and its application to RF noise modeling of MOSFETs"
H. Nah, M.S. Chae, H.S. Min, Y.J. Park, Proceedings of ISDRS 99, Charlottesville, Dec. 1-3, 1999

Talks and Presentations

 "An Integrated Multi-Channel Neural Recording System"
M.S. Chae, W.Liu, M. Sivaprakasam, BMES, Los Angeles, U. S, September 2007

 "Design Methodologye for an Integrated Low Power Neural Recording System"
M.S. Chae, W.Liu, G. Wang, M. Sivaprakasam, BMES, Chicago, U. S, October 2006